China’s top foundry is putting domestically built chipmaking tools on trial lines for artificial intelligence parts. It is not a leap to the technological frontier. It is a test of supply chain resilience. If the gear proves reliable at scale, Beijing gets a second-best route to compute that is independent of US and allied vendors.
Industry chatter in Shanghai points to SMIC running qualification on a broader slate of Chinese equipment sets for logic processes used in AI accelerators and networking silicon. The emphasis is on etch, deposition, clean, and chemical mechanical polishing tools—segments where local vendors have credible offerings. Names repeatedly cited by local media include AMEC in etch, Naura and Piotech in deposition, ACM Research’s Shanghai arm in wet clean and electrochemical plating, and Hwatsing for CMP. Photoresist coaters and developers from Kingsemi are also on more process flows. The immediate goal is to raise the share of domestic tools in mature and mid-node lines, then push them into denser designs produced with deep ultraviolet lithography.
The test is not single-machine performance. It is whether clusters of domestic tools can run stable recipes together at acceptable yields and uptime. AI chips magnify integration risks: larger dies, tighter interconnect layers, and heat budgets leave less room for variability. Even if early tool-of-record decisions land with local suppliers, the hurdle will be sustaining consistent output over quarters, not weeks. That is what customers want to see before signing volume orders.
This push is policy-backed. The 14th Five-Year Plan and MIIT work plans call for breakthroughs in core equipment, materials, and EDA to cut reliance on foreign suppliers. Big Fund III, a roughly 48 billion dollar vehicle launched this year, is structured to channel more capital to equipment and materials after earlier phases skewed to fabs. After high-profile graft probes in prior rounds, oversight has been tightened, with state asset managers tasked to track returns and project milestones more closely.
Capital deployment is accelerating. Industry trackers estimate China spent about 25 billion dollars on chipmaking tools this year, surpassing the combined outlays in South Korea, Taiwan, and the US. That surge is not only about building cleanrooms. It is about securing spares, service, and enough redundancy to ride out export curbs. NDRC’s push to expand national computing power hubs, paired with the “new quality productive forces” slogan, makes AI compute a public-good style priority. A supply chain that can support 28 to 7 nanometer-class logic via DUV, plus strong packaging, is acceptable for domestic AI workloads even if it lags global leaders.
The bottleneck remains lithography. ASML’s EUV tools are off limits. Certain advanced DUV immersion systems also face licensing. Chinese lithography maker SMEE has made progress at 28 nanometers and above, but its tools are not yet field-proven for high-volume production at the densities demanded by modern AI accelerators. The workaround is aggressive multi-patterning on DUV immersion to approximate 7 nanometer-class geometries. SMIC has demonstrated such capability for select chips. The economics are the constraint: multiple patterning increases mask counts, cycle time, and defect risks. It raises cost per good die and power consumption versus EUV-built equivalents at TSMC or Samsung.
That is why the current trials matter. If local etch, deposition, and metrology tools can tighten critical dimension control and cut variability across patterning steps, yields rise and DUV economics improve. Even then, parity is out of reach. But acceptable performance for domestic AI training—where model sizes are being tuned to fit available compute—is plausible. As a complement, advanced packaging that can stack or tile multiple chiplets can offset some density gaps.
Beijing is not betting on fabs alone. The strategy is to lift the entire stack where it can: accelerators, memory, packaging, and software. Huawei has re-emerged as the most significant systems player, iterating on its Ascend AI accelerators and releasing a high-spec smartphone processor built on a domestic flow. Even Nvidia’s CEO labeled Huawei a serious competitor in the China AI market. On the back end, OSATs such as JCET, Tongfu Microelectronics, and Huatian are expanding advanced packaging lines for high-power chips. China’s Achilles’ heel is HBM. Domestic DRAM producers are still multiple nodes behind and lack EUV; HBM-class output is nascent. Expect near-term reliance on imported memory where permitted, and a focus on alternative memory bandwidth solutions in system design.
EDA and materials are improving from a low base. Local EDA firms have traction in analog, RF, and parts of digital signoff. Materials vendors have expanded supply of specialty gases, slurries, and some photoresists. State media has highlighted “little giant” suppliers that carve out narrow leadership niches. The risk is dispersion: too many projects chasing the same milestone. The better programs co-locate vendors with fabs, embed service teams at lineside, and accept multi-year qualifications instead of racing for headline nodes.
Regulatory tactics are part of the playbook. China’s antitrust authority has reportedly opened a probe into Nvidia’s past Mellanox acquisition, a reminder that license to operate in the world’s second-largest data center market comes with conditions. Procurement guidelines at state entities and state-influenced clouds have quietly steered pilots toward domestic accelerators when feasible. The signal to foreign suppliers is clear: expect more compliance scrutiny and less pricing power.
Global markets are reading the tea leaves. Semiconductor equities sold off sharply in July on fears of tighter US export rules to China, underscoring how pivotal Chinese demand remains. Domestic A-share semiconductor equipment names have rallied on policy headlines and orders from state-backed fabs, but revenue recognition lags announcements. For allocators, the governance lesson is old: keep an eye on actual installed base, service revenue, and tool utilization, not just capex pledges. China’s own authorities appear to agree; after the graft shocks at the Big Fund’s earlier phases, the message from SASAC has emphasized return on net assets and hard KPI delivery by central SOEs.
Success for Beijing is not a 2 nanometer chip. It is a resilient, 70–80 percent localized tool chain for mature and mid nodes, a viable DUV-based path to 7 nanometer-class logic for select parts, and a packaging ecosystem that can integrate chiplets at scale. For SMIC and peers, that means domestic equipment share rising materially in 65 to 28 nanometer lines within 12–18 months, then taking selective sockets at 14 to 7 nanometers by 2026. Yields need to stabilize above the breakeven thresholds for large dies. Service and spare parts supply must be robust enough to keep OEE high.
On the system side, the objective is to ship enough credible AI accelerators to feed provincial computing hubs and major cloud providers. Power and cooling constraints will bind; AI data centers are already testing local grids. That puts energy efficiency on par with process node ambition. Policy will likely subsidize power, land, and depreciation via local governments as part of “new infrastructure,” but capex discipline will be tested if demand is cyclical.
Four markers will separate signal from noise. First, tool qualification: watch for domestic etch and deposition tools becoming tool of record in more SMIC and Hua Hong process steps, and for third-party metrology data that shows tighter variability. Second, Big Fund III disbursement cadence and co-investors: projects with anchor customers and co-located supply chains deserve a higher confidence score. Third, export control drift: any new US or allied restrictions on DUV services, spares, or advanced packaging could erode the economics of the DUV workaround. Fourth, procurement behavior at China’s top clouds and telcos: the speed at which they scale Huawei-based stacks will set the pace of domestic AI compute adoption.
The thesis is not complicated. China cannot buy its way to EUV, but it can spend, coordinate, and iterate its way to “good enough” AI compute built on DUV, domestic tools, and strong packaging. That outcome would blunt the impact of export controls, keep domestic AI training on track, and give policymakers leverage in a strategically important sector. For investors, the winners are likely to be boring industrials—toolmakers, materials suppliers, and packaging houses—that can execute quietly on multi-year service-heavy contracts.
